MA320002【PDF 74/208 页】MODULE PLUG-IN PIC32 USB OTG

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TABLE 4-31:

PORT F REGISTERS MAP FOR PIC32MX320F032H, PIC32MX320F064H, PIC32MX320F128H, PIC32MX340F128H,

PIC32MX340F256H AND PIC32MX340F512H DEVICES ONLY (1)

Bits

31/15

30/14

29/13

28/12

27/11

26/10

25/9

24/8

23/7

22/6

21/5

20/4

19/3

18/2

17/1

16/0

6140

6150

6160

TRISF

PORTF

LATF

31:16

15:0

31:16

15:0

31:16

15:0

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

TRISF6

—

RF6

—

LATF6

—

TRISF5

—

RF5

—

LATF5

—

TRISF4

—

RF4

—

LATF4

—

TRISF3

—

RF3

—

LATF3

—

TRISF2

—

RF2

—

LATF2

—

TRISF1

—

RF1

—

LATF1

—

TRISF0

—

RF0

—

LATF0

0000

07FF

0000

xxxx

0000

xxxx

6170

ODCF

31:16

15:0

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

— — — — — — — —

— ODCF6 ODCF5 ODCF4 ODCF3 ODCF2 ODCF1 ODCF0

0000

0000

Legend:

Note 1:

x = unknown value on Reset, — = unimplemented, read as ‘ 0 ’. Reset values are shown in hexadecimal.

All registers in this table have corresponding CLR, SET and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more

information.

TABLE 4-32:

PORT F REGISTERS MAP FOR PIC32MX420F032H, PIC32MX440F128H AND PIC2MX440F256H DEVICES ONLY (1)

Bits

31/15

30/14

29/13

28/12

27/11

26/10

25/9

24/8

23/7

22/6

21/5

20/4

19/3

18/2

17/1

16/0

6140

6150

6160

TRISF

PORTF

LATF

31:16

15:0

31:16

15:0

31:16

15:0

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

TRISF5

—

RF5

—

LATF5

—

TRISF4

—

RF4

—

LATF4

—

TRISF3

—

RF3

—

LATF3

—

TRISF2

—

RF2

—

LATF2

—

TRISF1

—

RF1

—

LATF1

—

TRISF0

—

RF0

—

LATF0

0000

03FF

0000

xxxx

0000

xxxx

6170

ODCF

31:16

15:0

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

— — — — — — —

— ODCF5 ODCF4 ODCF3 ODCF2 ODCF1 ODCF0

0000

0000

Legend:

Note 1:

x = unknown value on Reset, — = unimplemented, read as ‘ 0 ’. Reset values are shown in hexadecimal.

All registers in this table have corresponding CLR, SET and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more

information.

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